1. Technical Field
The embodiments described herein relate to a semiconductor circuit technology, in particular, to a semiconductor memory apparatus that easily produces a design model and increases the layout margin.
2. Related Art
The storage capacities of conventional semiconductor memory apparatus, such as SDR (Single Data Rate DRAM), DDR (Double Data Rate DRAM), DDR2, and DDR3, are increasing. Further, the data processing speeds are also increasing.
As these conventional semiconductor technologies, e.g., SDR, DDR, DDR2, and DDR3 are developed, the number of data bits that are read from or written to the memory cells corresponding to a single column during a single operation doubles. The column operation refers to the operation that selects a bit line crossing the activated word line and reads and writes data thereon.
Since the number of bit doubles so as to correspond to the column operation, signal lines through which data is input and output and the circuit components for controlling the column operation correspondingly double.
A conventional semiconductor memory apparatus includes a memory cell that consists of transistors connected to bit lines and word lines, a bank that consists of circuits for reading data from and writing data to the memory cell, and a peripheral circuit that inputs data from outside the semiconductor memory apparatus into the bank and outputs data from the bank to the outside.
The number of banks varies depends on the memory capacity of the semiconductor memory apparatus.
For example, a conventional semiconductor memory apparatus, e.g., an X16 DDR3, has one bank that is divided into eight small sections Octet0 to Octet7, as shown in FIG. 1.
The eight small sections Octet0 to Octet7 have the same configuration. For example, Octet0 includes a cell area 11, a column control unit 12, and an IO sense amplifier (hereinafter, referred to as IOSA) 13.
The column control unit 12 receives a column control signal YAE to generate a column selection signal CY<i>.
The IOSA 13 detects and amplifies data of a local IO line LIOT/LIOB and outputs the data through a global IO line GIO_0.
The operation of such a conventional semiconductor apparatus will be described with reference to FIG. 2.
When a read command Read is input, the column control signal YAE is generated after a predetermined time.
The column control units 12 of the small sections Octet0 to Octet7 delays the column control signal YAE by a predetermined time, and output the column selection signal CY<i> to the individual cell areas 11.
Data that is stored in the cell areas 11 of the small sections Octet0 to Octet7 are simultaneously transmitted to the individual global IO line GIO_0 to GIO_7 through the local IO lines LIOT/LIOB and IOSA 13.
The data of the global IO lines GIO_0 to GIO_7 is output to the outside of the semiconductor memory apparatus through pads PAD (not shown), on the basis of the strobe signal DQS.
In such a conventional semiconductor apparatus, each of eight small sections Octet0 to Octet7 includes a local IO line LIOT/LIOB, a column control unit 12 and an IO sense amplifier 13. Further, the global IO lines are provided individually for every small section Octet0 to Octet7.
As described above, a conventional semiconductor memory apparatus necessarily includes a signal line and a column control unit for every small section, which makes the circuit design and the layout design be difficult. Further, as the semiconductor memory technologies develop, larger memory capacity is required along with faster data processing performance using circuits that occupy smaller than or equal to the same area required in conventional apparatus. Therefore, the difficulty in the circuit design and the layout design may become worse.